In recent years, for environmental and cost reasons, interest has grown in optical component modules having low power consumption and low thermal dissipation. One application of such modules is in Erbium Doped Fibre Amplifier (EDFA) designs, in which the pump module is one of the biggest contributors to the power consumption and heat dissipation.
Heat is generally removed from such modules using a Thermoelectric Cooler (TEC). A TEC is a solid-state active heat pump device which uses the Peltier effect to transfer heat from one side of the device to the other side against the temperature gradient (from cold to hot), with consumption of electrical energy. The effectiveness of the pump at moving the heat away from the cold side is dependent upon the current provided and how well the heat can be removed from the hot side. The heat transfer is also dependent on the temperature difference (ΔT) between the hot side and the cold side. More current must be provided to provide effective cooling when ΔT is large.
In the case of optical modules such as those used in EDFA designs, heat is usually transferred from a carrier, in which a chip is mounted, to the casing or package in which the module is contained. The temperature of the casing is usually higher in use than the temperature of the chip, and a TEC is therefore required to effect the heat transfer. The current to the TEC is generally controlled by a feedback loop so that the chip is maintained at a desired target temperature. In order to optimise the power consumption of the TEC, it is desirable to prevent the temperature difference ΔT between the casing temperature and the Chip on Carrier (CoC) temperature from becoming too large.
One way of achieving low TEC power consumption is to set the target CoC temperature to a high value (e.g. 40° C.). This ensures that ΔT will be small even for high casing temperatures, and the design thus achieves low power consumption and heat dissipation even at such high casing temperatures. The disadvantage with this approach is that it greatly increases the chip failure rate (FIT rate), which depends on the chip temperature. For example, the FIT rate at 40° C. is double that at 25° C.
One way to overcome this problem is to use an algorithm to adjust the target CoC temperature when the casing temperature of the package gets very high. One way of achieving this is described in U.S. Pat. No. 7,512,162. However, this is difficult to design and implement.
It would therefore be desirable to achieve a lower TEC power consumption with minimum impact on FIT rate, and without the need for complex designs.